Timing control circuit for electronic fuel injection system

ABSTRACT

A digital circuit is provided for establishing the proper time for supplying a control signal, for example, for firing a fuel injector. The circuit operates primarily upon timing signals from the distributor (as well as a pulse width computer) to determine the proper sequence and timing arrangement for supplying the control signals.

'United States Patent [191 Watson et a1.

[ Oct. 21, 1975 TIMING CONTROL CIRCUIT FOR ELECTRONIC FUEL INJECTION SYSTEM [75] Inventors: George A. Watson, Tustin; John J.

Bollinger, Orange, both of Calif.

[73] Assignee: Rockwell International Corporation, El Segundo, Calif.

[22] Filed: Apr. 25, 1973 [21] Appl. No.: 354,296

[44] Published under the Trial Voluntary Protest Program on January 28, 1975 as document no. B 354,296.

3,644,718 2/1972 Osborne et a1. 235/92 CC 3,652,832 3/1972 Baumann 235/92 T 3,716,703 2/1973 Gordon 235/92 CC 3,790,720 2/1974 Schartmann 235/92 FQ Primary Examiner-Gareth D. Shaw Assistant Examiner-Joseph M. Thesz, Jr. Attorney, Agent, or FirmH. Fredrick Hamann; G. Donald Weber, Jr.

[ 57] ABSTRACT A digital circuit is provided for establishing the proper time for supplying a control signal, for example, for firing a fuel injector. The circuit operates primarily upon timing signals from the distributor (as well as a pulse width computer) to determine the proper sequence and timing arrangement for supplying the con- [56] References Cited trol signals.

UNITED STATES PATENTS 3,209,130 9/1965 Schmidt 235/92 F0 21 Claims, 4 Drawing Figures ANALOG PULSE TO WIDTH SENSORS DIGITAL comm-ER CONVERTER n PW l PULSE GENERATORS DRIVERS lNrECTDRS z x Ma ION TIMING DISTRIBfiTOR DETECTORS CONTROL US. Patent Oct.21, 1975 Sheet10f3 3,914,580

FIG.3

w wa -s SENSORS DIGITAL coMPurER CONVERTER IO PULSE GENERATORS DRIVIERS lmsc' roas l6 DISTRIByTOR DETECTORS ROL I I5 I3 l4 FIG.|

INC

RESET oovm COUNTER DEC (TO H64) OFT US. Patent Oct. 21, 1975 Sheet30f3 3,914,580

A SUBTRACT B A-B REF DECODER 6| COMPARE PW AZB FIR FIG. 4

TIMING CONTROL CIRCUIT FOR ELECTRONIC FUEL INJECTION SYSTEM BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to control systems particularly associated with fuel injection systems. In particular, the invention relates to fuel injection systems including electronic controls for controlling a pulse width or time duration. It is known that use of fuel injection systems instead of carburetors for engines with controlled ignition results in a certain number of advantages which are based on the greater possibilities for regulation and for adaptation to the particular type of engine. It is, thus, possible to lower the fuel consumption, to increase the power, and above all to reduce the percentage of unburned matter in the exhaust gas, especially the hydrocarbons, oxides of nitrogen and carbon monoxide. This latter advantage is of great importance to alleviate air pollution problems.

The use of conventional injection pumps and systems known in the art, is generally quite expensive. Moreover, these conventional systems have tolerance problems and exhibit generally sluggish operation. Many fuel injection systems have been proposed. Typical examples of such systems are represented in U.S. Pat. Nos. 3,456,628 and 3,710,763 to J. Bassot et al., entitled High Speed Fuel Injection System, and U.S. Pat. No. 2,980,090 to R. W. Sutton, entitled Fuel Injection System. The systems disclosed in these patents demonstrate some of the techniques known in the art. However, these systems will have shortcomings. Therefore, new and improved systems are required. The new systems use sophisticated electronic control systems, especially of the type adaptable to MOS/LS1 techniques.

SUMMARY OF THE INVENTION This invention relates to a circuit for establishing the appropriate timing and sequence of application of control signals to a utilization device. The circuit detects signals from a free running source (e.g., a distributor) which is representative of the operation of a utilization device, such as an engine. The circuit obtains these signals, identifies the signals and produces output signals representative thereof. The signalsare used to establish proper ordering and timing of output control signals. The ordering and timing of the signals produced by the circuit will vary as a function of operational parameters of the utilization device as determined or dictated by the free running signal circuit.

BRIEF DESCRIPTION OF THE DRAWINGS DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. I, there is shown a block diagram of the electronic control portion of a fuel injection system. Many of the electronic components used in this system are known in the art. Specific detailed descriptions of these components are, therefore, not presented herewith. Obviously, those skilled in the art will be able to choose the particular configuration of the individual components as a function of the remainder of the circuit, the type of construction, and so forth. I

Sensors 10 may represent one or more sensors such as thermistors, strain gages, potentiometers, or the like which are capable of detecting ambient or environmental conditions such as temperature, pressure, position, and the like. Sensors 10 are connected to analog to digital (A/D) converters 11. The analog signals produced by sensors 10 are converted by A/D converters 11 into digital signals. The digital signals from A/D converters 11 are supplied to pulse width computer 12. The pulse width computer 12 represents the particular invention shown and described herein. The specific configuration of this counter is discussed in detail subsequently. Computer 12 supplies signals to pulse generator 16 as described hereinafter.

Distributor 13 is a standard distributor usually found in any automotive-type vehicle augmented with a second set of points to establish a reference or identification signal once each engine cycle. Actually, distributor 13 may represent any type of signal generating device the output signal of which is functionally related to engine shaft angle. This output signal represents the operation of the unit involved. For example, in this embodiment, distributor 13 is arranged to supply pulses for each engine cycle (to establish a reference position) and for each individual cylinder cycle. For example, an eight cylinder engine will produce eight individual distributor signals as well as one engine cycle signal, per engine cycle. In other cases, it may be desirable or suitable to obtain this type of signal from a crank shaft or other representative location.

The signals generated by distributor 13 are supplied to detectors 14 which may be any suitable type of detector such as reed relays, magnetic sensors, logic gates, or the like. The detectors operate upon the signals supplied by distributor 13 to produce an output signal representative of the distributor operation and, thus, the timing arrangement of the device (i.e., engine operation).

Injection timing control 15 is connected to receive signals from detectors 14. Injection timing control 15 operates upon these signals and produces control signals which further control and indicate the operation of the overall device. For example, control circuit 15 may ultimately control the firing of injector drivers and the like. The timing control signals are generated as a function of the device operation as described in greater detail in co-pending application of G. A. Watson, et al. entitled Fuel Injection Pulse Width Computer, bearing I Ser. No. 354,294, filed on Apr. 25, 1973, and assigned other utilization device) to control the operation thereof.

Thus, it is seen that the signals applied to driver 17 and utilization device 18 are functions of pulses supplied by generator 16. Generator 16 supplies pulses which are a function of the actual speed of operation of the utilization devices as established by distributor l3, detectors 14 and control circuitry 15. In addition, the pulses are functions of other factors such as temperature, pressure, and the like, which are detected by sensors and converted by A/D converters 11 into digital signals which are operated upon by computer 12. This overall system arrangement is relatively standard in the art and does not represent the invention,

per se.

Referring now to FIG. 2, there is shown a logic diagram for one embodiment of the delay logic circuitry used in the injection timing control circuitry shown in FIG. 1. A suitable source 38 such as a battery or the like is connected to delay circuit 24 via switch 39. The output terminal of delay circuit 24 is connected to the reset terminal of a plurality of flip-flops as shown. For example, the Power On Reset signal (POR) is supplied from delay 24 to the reset terminal of flip-flop 20.

The data input terminal of copy or D-type flip-flop is connected to receive the IDENT signal from source 40 of distributor signals (DIST. SIG.). Source 40 represents a source of distributor signals and may include distributor 13 and detector 14 of FIG. 1. The IDENT signal occurs once per engine cycle and establishes a reference point in the cycle. A clock signal (C) is supplied to the clock input terminal of flip-flop 20 by a suitable clock source (not shown). Clock signal (C) exhibits a frequency greater than the frequency of the sig-' nals supplied by source 40. For example, clock signal (C) may be applied at a frequency of 2OKHZ.

Flip-flop 20 is a type of flip-flop frequently referred to as a copy or D-type flip-flop. That is, the signal applied to the data input terminal D is transferred to the Q output terminal upon the application of a clock signal. Thus, these flip-flops transfer the input signal to the output terminal at the leading (i.e., positive going) edge of the clock signal. Consequently, the flip-flops operate as delay flip-flops.

The 0 output terminal of flip-flop 20 is connected to the data input terminal D of flip-flop 21 as well as to one input of AND gate 22. The clock signal terminal of flip-flop 21 is connected to receive clock signal (C). The reset terminal R of flip-flop 21 is connected to receive the POR signal from delay circuit 24. The Q output terminal of flip-flop 21 is connected to the other input terminal of AND gate 22. The output terminal of AND gate 22 produces the signal RP, a one clock timesignal occurring at the positive transitions of IDENT, and is connected to the K input terminal of .l-K flip-flop 23. The clock terminal of flip-flop 23 receives clock signal (C). The J input terminal as well as the set terminal of flip-flop 23 are both connected to receive the POR signal from delay circuit 24. The Q output terminal of flip-flop 23 provides the CLEAR signal which is supplied to flip-flops shown and described relative to FIG. 3.

Another signal from source 40, viz. the signal DIST, is supplied to the data input terminal of copy flip-flop 25. The DIST signal represents the actual signals generated by the distributor and includes one or more signals for each cylinder. The clock terminal of flip-flop 25 is connected to receive clock signal (C). The reset terminal of flip-flop 25, along with the reset terminal of flipflop 26, is connected to receive the POR signal from delay circuit 24. The Q output terminal of flip-flop 25 is connected to the input terminal of copy flip-flop 26 and to one input terminal of AND gate 27. Clock signal (C) is supplied to the clock terminal of flip-flop 26. The Q output terminal of flip-flop 26 is connected to the other input of AND gate 27. AND gate 27 produces the output signal DP, which is a one clock time signal occurring at the positive transitions of DIST. The output terminal of gate 27 is connected to the increment input of reference counter 28. The reset input of reference counter 28 is connected to receive the signal RP from gate 22. The clock signal (C) is connected to the clock terminal of reference counter 28. Reference counter 28 which may be a multibit counter, produces the multibit output signal REF which is supplied to the circuit shown in FIG. 3.

The signal DP from gate 27 is also connected to the reset input terminal of counter 29 which may be another multibit counter. The clock terminal of counter 29 receives the clock signal (C). The increment input terminal of counter 29 is connected via inverter 30 to the output terminal of AND gate 31. The input terminals of AND gate 31 are connected to the output terminals of counter 29 and receive the multibit signal designated as signal DT. The output signal from AND gate 31 is also connected to the data input terminal of copy flip-flop 34. The set terminal of flip-flop 34 is connected to receive the reset signal POR. The clock terminal of flip-flop 34 is connected to receive the signal DP from gate 27. The Q output terminal of flipflop 34 produces CRANK and is connected to one input terminal of AND gate 35. Another input terminal of AND gate 35 is connected to the output terminal of digital comparator 33. One set of input terminals (A) of digital comparator 33 is connected to receive the multibit signal DT from digital comparator 29. These same signals are supplied to input terminals of state detector 32 which produces an output signal DF'I which is supplied to the circuitry shown in FIG. 3.

The other set of input terminals (B) of digital comparator 33 receives the DT signals from threshold memory 36. The address input terminal of threshold memory 36 receives the multibit DELAY signal produced at the output terminal of threshold counter 37. The DELAY signal is also supplied to other circuitry shown in FIG. 3.

The reset terminal of threshold counter 37 is connected to receive the signal DP from gate 27. The increment input terminal of threshold counter 37 is connected to the output of AND gate 35 discussed supra. The clock terminal of threshold counter 37 is connected to receive the clock signal (C).

AND gate 35 receives the output signal from digital comparator 33 as well as the PWOK output signal from digital comparator 138. Digital comparator 138 receives, as one input signal on the A set of input terminals, the signal PW from the pulse width computer 12 shown in FIG. 1. A detailed description of pulse width computer 12 is incorporated by reference to the aforementioned copending application of G. A. Watson et al. Digital comparator 38 also receives, at the B set of input terminals, the signal PW from source 42.

In operation, the circuits shown in FIG. 2, essentially control a DELAY output signal as described hereinafter. In order to initiate operation of the circuit, power source 38 is applied to the circuit by closure of switch 39 as for example by activating the ignition of an automobile. DELAY circuit 24 insures that the critical elements of FIG. 2 assume a proper start up state after power is applied. This delay permits any transients which might occur to be terminated or damped by any suitable circuitry or the like. Moreover, this delay assures that all of the logic circuits included in the overall circuitry have been properly energized and are in a condition to receive the reset signal. The POR signal provided by DELAY circuit 24 causes each of the flipflops which receive this signal to be set or reset to an intiial condition. Perhaps the most important initialization function produced by signal POR is to cause flipflop 23 to assume the condition wherein output signal CLEAR is produced. The CLEAR signal is supplied to the circuitry shown in FIG. 3 (and described subsequently), whereby the injector drivers and, thus, the fuel injectors in the system are maintained in the off condition until the first IDENT pulse is produced.

Meanwhile, the distributor signals from source 40 are supplied to flip-flops and 25, respectively. In particularly, the DIST signal continuously supplied to flipflop represents each pulse produced by the distributor during its operation. For example, in an eight cyclinder engine, eight pulses per engine cycle would typically be applied to flip-flop 25. In a six cylinder engine typically only six pulses per engine cycle would be supplied thereto. Of course, other pulse rates can be achieved and the pulses may be supplied by a crank shaft sensor or the like. Conversely, through any suitable means (i.e., distributor, crank shaft sensor or the like) an identification signal IDENT is supplied to flipflop 20. Only one IDENT signal is typically detected for each engine cycle and is utilized to permit synchronization of the distributor and the engine cycle operation. Thus, by detecting the IDENT and the DIST signals, the particular firing order for the fuel injectors in the engine is determined. Moreover, the instantaneous relationship of the distributor pulses and, thus, the engine cycle operation is determined.

The operation of flip-flops 20, 21, 23, 25, 26 and 34 is such that signal POR sets or resets each of these flipflops to an initial condition. The set signal causes flipflop 23 to produce a high level or true output signal. Consequently, the CLEAR signal is supplied to the injector drivers and/or injectors, to render the injectors inoperative.

In addition, the reset signal POR causes flip-flop 20 to produce a low level or false signal at the Q output terminal thereof. Conversely, a high level or true output signal is produced at the Q output terminal of flipflop 21. As a result, AND gate 22 receives only one high level or true signal as well as one low level or false signal. (Incidentally, the terms high level, positive, binary or true are used interchangeably in this discussion. Similarly, the terms low level, negative, false, or binary 0 are used interchangeably also. No designation of positive or negative voltage levels is specified or imsignal. After POR goes false, the flip-flops respond to the clocked input signals.

When IDENT signal is supplied by source 40, a high level or true signal is supplied to the D input terminal of flip-flop 20. The next clock signal (C) applied to the clock input terminal of flip-flop 20 causes the positive signal at the data input to be transferred through to the Q output on the leading edge of the clock signal. Consequently, a binary 1 or true signal is supplied from the Q output of flip-flop 20 to the data input of flip-flop 21 and to one input terminal of AND gate 22. As indicated supra, the Q output of flip-flop 21 is, concurrently, producing a high level signal. Since the input signals supplied to all of the input terminals are high level or binary l signals, AND gate 22 produces a high level output signal RP. This signal is supplied to the reset terminal of reference counter 28 and to the K input terminal of flip-flop 23. Consequently reference counter 28 is reset to zero and on the next clock signal (i.e., CLEAR) the output signal supplied by the Q output of flip-flop 23 switches to a low level signal. Thus, the various injectors are placed in a condition to receive control or firing signals as described subsequently.

Meanwhile, as suggested supra, source 40 has been continously supplying the DIST signal to the data input terminal of flip-flop 25. Again, upon the application of clock signal (C) the high level DIST signal has been transmitted from the input terminal D to the Q output terminal of flip-flop 25. In addition, this signal has also been applied to one input terminal of AND gate 27. Meanwhile, flip-flop 26 continues to reside in the false condition established by reset signal POR. During this one clock time the output signal DP from AND gate 27 is true since both of its inputs are true. However, the next clock pulse (C) causes flip-flop 26 to copy the Q output of flip-flop 25 which is a true signal. The Q output of flip-flop 26 becomes false causing signal DP from AND gate 27 to become false. Flip-flop 25 and 26, in conjunction with AND gate 27, form a one clock time edge detector for the DIST signal. That is, each time the DIST signal makes a transition from false to true, the DP signal produces a true signal for one clock time.

The digital pulse signal DP is supplied to the increment input terminal of reference counter 28. Reference counter 28 is adapted to count the DP signals. This is effected by applying clock pulses (C) to the clock input terminal of counter 28. Since DP is true for only one clock time for each DIST signal, counter 28 increments only once for each DIST signal. In the preferred embodiment, counter 28 counts modulo n where n is the number of DIST signals in an engine cycle. Reference counter 28 produces the output signal REF which is supplied to FIG. 3 as discussed infra. Output signal REF is a function of the number of DP pulses counted by counter 28. Thus, counter 28 is reset to a particular condition, for example but not limited to zero, by each RP signal. Thereafter, counter 28 is incremented by each clock pulse (C) which occurs concurrent with a DP signal to produce output signal REF which effectively establishes the distributor or cylinder position which is to be acted upon.

In addition, the signal DP is supplied to the reset terminal of timer 29. Thus, timer 29 which is in effect, a counter, is reset to zero by each distributor pulse DP. In effect, timer 29 counts at the clock frequency until the next DP signal which resets timer 29 to zero. Conversely, if a DP signal is not timely provided, timer 29 reaches a particular high count which, in this embodiment is signified by an output signal DT comprised of all binary ones. When this count is achieved, the increment or advance input signal goes false. That is, the output signal DT from timer 29 is supplied viaAND gate 31 to inverter 30 which is returned to the increment terminal of timer 29. When each of the signals in the multibit output signal DT is a binary 1, AND gate 31-produces a positive or true output signal. Inverter 30 operates upon this true signal and produces a false signal which is supplied to the increment terminal of counter 29. The application of the false or binary zero signal to the increment terminal of timer 29 has the effect of preventing additional counting of the clock signal (C) by timer 29. Therefore, the all ones condition at signal DT is maintained until thenext DP signal resets timer 29.

The true DT signal is supplied to the data inputterminal D of flip-flop 34 as well as to the input terminal of inverter 30. If AND gate 31 supplies a true signal to the D terminal of flip-flop 34 concurrently with a DP pulse, CRANK flip-flop 34 will be set true and will remain true until the signal supplied by AND gate 31 is false concurrently with a DP pulse. The CRANK flip-flop 34 willthen be set false.

The CRANK flip-flop is caused to be set true when the length of time between DP pulses is sufficiently large to allow the timer 29 to reach the particular state that enables AND gate 31. This indicates that the engine RPM is less than some predetermined threshold. The particular timer state is chosen so that the predetermined RPM threshold is just above the maximum cranking RPM. The CRANK flip-flop, therefore, indicates that the engine is cranking or stopped.

The Q output of the CRANK flip-flop 34 becomes false when the CRANK flipflop is set true as discussed supra. The false signal at Q (i.e., CRANK signal) of flip-flop 34 prevents AND gate 35 from producing a true signal which in turn prevents the increment input signal to counter 37 from becoming true. Since CRANK flip-flop 34 is clocked by the same signal that resets counter 37, the CRANK flip-flop becoming true will preclude counter 37 from counting beyond the reset state.

State detector 32 logically decodes a particular state of timer 29 which occurs a fixed number of clock pulses and hence a fixed period of time after each DP pulse. When this particular state is detected, detector is utilized in the circuitry shown in FIG. 3 to be described infra.

The operation of the circuit included in the instant invention is based on the theory that several ranges of RPM or engine speed can be established. These ranges are pertinent to engine operating parameters and characteristics. This information is utilized in determining the time of firing of an injector relative to the time of opening of the intake valve for a particular cylinder. Clearly, if the engine is operating relatively slowly, the intake valve is open for a relatively long time period and the fuel to be injected therein can readily be properly injected. Conversely, when the engine is operating relatively rapidly, the intake valve is open for a relatively short time and the fuel must be injected into the system earlier in order to assure that fuel reaches the intake valve at the appropriate time to achieve proper combustion. For convenience, typical speed ranges are established between the limits listed herewith.

DELAY RPM RANGE 4500 to 3000 to 4500 2000 to 3000 1200 to 2000 700 to 1200 0 to 700 Obviously, other ranges or limits can be established if so desired.

Moreover, in the instant invention, the ranges are identified numerically in order that a numerical (e.g., binary) designator can be applied thereto. The appropriate designator or number is ascribed to each range. By operating upon the time period between distributor pulses, DP, the speed range can be detected and appropriate modifications of the various circuit operations can be effected.

The speed range parameters are obtained, by inter alia, comparing the pulse width signal PW from pulse width computer 12 with a pulse width threshold signal PW from a suitable source 42. Source 42 may be any suitable source, such as a fixed memory, for producing a fixed signal representative of a prescribed time period, for example 20 milliseconds. This signal represents the time duration of the pulse width and establishes the limit therefore.

The signal PW from pulse width computer 12 is determined in accordance with any suitable computer for producing a signal representative of the pulse width for the injector signal. A circuit which may be utilized to produce this type signal is described in co-pending application of G. A. Watson et al noted supra.

The PW and PW signals are supplied to digital comparator 138. Digital comparator 138 produces at the output terminal thereof the output signal PWOK. This signal is applied as one input to AND gate 35 which is discussed hereinafter. When the signal PW is greater than signal PW, signal PWOK is true or a binary 1. Conversely, signal PWOK is false when signal PW is greater than signal PW- When signal PWOK is a binary l, the engine is operating at a relatively high rate of speed, i.e., greater than cranking speed. This binary signal essentially enables gate 35 whereby an incrementing signal can be applied to counter 37 if other conditions warrant.

Threshold counter 37 is connected to receive the DP signal and is reset to zero by each DP signal. In the absence of an incrementing signal from gate 35, the output signal (DELAY) supplied by threshold counter 37 is zero and represents zero delay. The DELAY signal is applied to circuitry in FIG. 3 and described infra. In addition, the DELAY signal is applied to threshold memory 36. The DELAY signal supplied from counter 37 is utilized to address a memory location in threshold memory 36. This memory contains thresholds which ascend as the DELAY address ascends and produces output signal DT which signal represents a particular engine speed range as previously discussed. As timer 29 counts, DT may exeed DT (i.e., A is greater than B) whereby comparator 37 produces a binary 1 output signal. This signal also enables gate 35 whereby an incrementing signal is supplied to counter 37 if other conditions warrant. If counter 37 is incremented, the next DT range is addressed (which is higher than the previous) until DT again exceeds DT At the time of the next DP pulse, but prior to counter 37 being reset, the DELAY output of counter 37 represents the RPM range in which the engine is operating.

As indicated supra, the output signal from AND gate 31 is connected to the data input terminal of flip-flop 34. Flip-flop 34 is clocked by each DP signal. The output signal from flip-flop 34 remains positive or a binary so long as the DT signal represents an output signal of all binary ones from timer 29. That is, this signal is previously properly scaled, in this embodiment, so that the all ones condition is reached only when the engine speed is sufficiently less than idle so that the engine must be off or cranking. When gate 35 receives all binary l signals from flip-flop 34, comparator 38 and comparator 33, a positive signal is applied to the increment input terminal of counter 37. Thus, counter 37 is incremented (i.e.. the count therein is increased) with the application of a clock signal (C).

Thus, it is seen that gate 35 is enabled by the application of all binary 1 signals thereto. The binary 1 signals represent the conditions wherein the engine is operating (PWOK), above the cranking speed (CRANK) and at a higher speed than indicated by the previous speed range (DT When gate 35 is enabled, counter 37 is incremented and produces a higher DELAY signal whereby threshold memory 36 produces a higher DT signal. This operation continues until one (or more) of the signals supplied to gate 35 becomes a binary 0. This binary 0 signal indicates that the engine is operating within the defined speed range wherein no additional delay is required in the firing of the injectors. Referring concurrently to FIGS. 3 and 4, there is shown a block, logic diagram of the tire control and injector control logic circuit. The distributor pulses DP are supplied to one input terminal of each of AND gates 50, 54, and 58. The other input terminal of AND gate 50 is connected to one output terminal of digital comparator 52.

- The other input terminal of AND gate 58 is connected to another output terminal of digital comparator 52. The output terminal of AND gate 50 is connected to the incrementing input terminal of up/down counter 51. The reset terminal of counter 51 receives the POR signal while the clock input terminal of counter 51 receives the clock signal (C). The decrementing input terminal of counter 51 is connected to the output terminal of AND gate 56 described hereinafter.

The output terminal of counter 51 is connected to one input terminal of subtractor circuit 60 (FIG. 4) as well as to the A input terminal of digital comparator 52. The B input terminal of digital comparator 52 is connected to receive the DELAY signal from counter 37 in FIG. 2. Digital comparator 52 compares the SERVO and DELAY signals and produced output signals representative of the comparison result. When the DELAY signal is greater than the SERVO signal, a binary l signal is supplied to AND gate 50 as well as to an input terminal of inverter 53. Conversely, when the SERVO signal is greater than the DELAY signal, a positive signal is supplied to AND gate 58.

The output terminal of inverter 53 is connected to one input terminal of AND gate 54. The other input terminal of AND gate 54 is connected to receive the distributor pulse signal DP. The output terminal of AND gate 54 is connected to one input terminal of OR gate 55.

The output terminal of AND gate 58, noted supra, is connected to the J input terminal of .l-K flip-flop 57. The clock terminal of flip-flop 57 is connected to receive the clock signal (C). The 0 output terminal flipflop 57 is connected to one input terminal of AND gate 56. The DFT signal from state detector 32 in FIG. 2 is supplied to another input terminal of AND gate 56. The output terminal of AND gate 56is connected to the K input terminal flip-flop 57, to a second input terminal of OR gate 55 and to the decrementing input terminal of up/down counter 51. The output terminal of OR gate 55 is connected to supply the FIRE signal which is connected to AND gate 66 through 67 as described hereinafter.

As suggested supra, subtractor 60 receives the REF signal from counter 28 in FIG. 2. In addition, subtractor 60 receives the SERVO signal from up/down counter 51. The output terminals of subtractor 60 are connected to input terminals of decoder 61. Decoder 61 is a one-of-N decoder where N is the number of injectors and injector drivers to be utilized, for example, N 8. One input terminal of each of gates 66 through 67 (which represents two of N AND gates) is connected to a separate one of the N output terminals of decoder 61. The other terminal of each of gates 66 through 67 is connected in common to the output ter minal of OR gate 55 to receive the FIRE signal. The output terminals of gates 66 and 67 are connected to the J input terminals of .I-K flip-flops 68 and 69, respectively (which represent two of N flip-flops).

The PW, or pulse width, signal from the pulse width computer 12 of FIGS. 1 and 2 is supplied to the B input terminals of digital comparators 62 and 64 (which represent two of N digital comparators). The A input terminals of digital comparators 62 and 64 are connected to the output terminals of counters 63 and 65, respectively. The incrementing input terminal of counter 63 is connected to the Q output terminal of flip-flop 68. The Q output terminal of flip-flop 68 is connected to the reset input terminal of counter 63. The clock terminal of counter 63 is connected to receive the clock signal (C). The interconnections between flip-flop 69 and counter 65 are similar to those connections made between flip-flop 68 and counter 63. In addition, the CLEAR signal from flip-flop 23 in FIG. 2 is connected to the CLEAR or reset terminals of flip-flops 68 and 69, respectively.

Basically, the FIRE logic circuit shown in FIG. 3 generates FIRE pulses which turn on the respective injectors at the proper time in the engine cycle based on pulse width PW and engine RPM. In other words, as the vehicle is in operation, sudden changes in speed could cause the pulse width signal PW to vary. As suggested supra, threshold counter 37 operates to produce a specific signal which addresses the threshold memory 36 and produces a signal representative of a particular speed range. A sudden change in speed could cause threshold memory 36 to produce an additional (or insufficient) range signal. The signal could then, while recirculating through the circuit, cause a DELAY signal pulse of improper information. For example, suppose the vehicle was operating in a particular range such as speed range 1. This speed range would cause a DELAY signal to be generated which causes the FIRE pulses to be triggered by a distributor pulse which is representative of, for example, the distributor pulse for cylinder two. If now, the vehicle speed changes such that it is operating in a speed range which requires the pulse to be triggered by the distributor pulse for cylinder one, it is obvious that the distributor pulse for cylinder one has already passed and it would be impossible to FIRE the injector to assure that fuel was injected into the appropriate cylinder at the appropriate time.

Conversely, if the situation were reversed the system could conceivably attempt to FIRE the same injector twice during an engine cycle wherein twice as much fuel would be applied to a particular cylinder as is required.

In the following descriptive example, engine cylinders are numbered in the order that they are ignited. Thus, when the engine operating condition calls for an injection timing delay of zero (i.e., DELAY at the end of a DP interval), the FIRE logic circuit generates FIRE and SERVO signals so that the injection for cylinder one is initiated by the distributor pulse for cylinder one, two for two, three for three, and so forth.

Further, if engine operation calls for a delay of one distributor pulse prior to injection (i.e., DELAY l at the end of a DP interval), then FIRE and SERVO signals are produced so that the injection for cylinder one is initiated by the distributor pulse for cylinder two, two for three, three for four, and so forth. The relationship for larger delays can be readily inferred.

Logic elements 50, 51, 52, 53, 54, 55, 56, 57 and 58 insure that one and only one injection occurs per cylinder per engine cycle, particularly as the delay changes due to changes in engine operation.

One of the major purposes in having electronic fuel injections is to permit non-polluting engines. Thus, it is very important for low emission and high quality performance that each cylinder be injected once and only once during an engine cycle. Consequently, the actual delay to be used to fire the injector is servoed with a computed delay in a manner such that changes in delay can be controlled. However, the rate of change of delay is limited to one per distributor pulse. As will be seen, in steady operation there is one injection of fuel per distributor pulse DP. However, when the delay decreases by one distributor pulse of engine angle, two injectors are fired during one distributor pulse interval. This has the net effect of changing the delay by one distributor pulse. Conversely, when the delay increases by one distributor pulse of engine angle, there is a distributor pulse interval when no injectors are fired.

In addition, it is determined that the driver circuits for the injectors have a recovery time which must be observed. That is, each time an injector is turned on by application of a signal to the injector driver, a finite recovery time must be provided before another injector can be turned on. This restriction is included in the logic operation of the circuits shown in FIG. 3.

In operation, the POR signal is supplied to counter 51 to reset the counter to the zero state. Consequently, the output SERVO signal is zero. Subsequently, the distributor pulse signal DP is applied to AND gates 50 and 58. So long as the DELAY signal and SERVO signal remain the same, i.e., remain identical, a B greater than A, or A greater than B, condition in digital comparator 52 does not occur. Consequently, neither gate 50 nor gate 58 is enabled. Consequently, the SERVO signal remains at the zero state. This state is the same as the zero delay which is generated by threshold counter 37 and indicative of the zero speed range.

As a result, if the DELAY is the same as the SERVO, the SERVO signal remains unchanged. Thus, a FIRE signal or command is generated by a distributor pulse signal DP. That is, inverter 53 receives a false input signal from digital comparator 52. This signal is inverted and a true signal is supplied to AND gate 54 which is enabled thereby. Thus, as the DP signals are supplied to AND gate 54 and substantially identical signals are supplied to OR gate 55, and substantially identical signals are supplied to OR gate 55, the FIRE signal from OR gate 55 is produced as a result.

If, as a result of a change in engine operation, the DELAY signal becomes larger than the SERVO signal, a binary one is produced at the B greater than A output terminal of digital comparator 52. This signal is applied to enable AND gate whereby the next DP.signal is supplied to the incrementing terminal of up/down counter 51. Consequently, the SERVO signal is incremented by one but a FIRE command is not generated. That is, the B greater than A signal, i.e., binary one, is inverted by inverter 53 wherein AND gate 54 is disabled and the DP signal is not transmitted therethrough. Consequently, during this particular time period, i.e., portion of the engine cycle, no injector is fired.

If, on the other hand, the DELAY signal becomes less than the SERVO signal, a FIRE command or signal is generated by OR gate 55 and DELAY FIRE flip-flop 57 is set to the one condition. That is, when the A greater than B condition exists a binary one signal is applied to enable AND gate 58. Consequently, the next DP signal passes through AND gate 58 and is applied to the J input of flip-flop 57. At the next clock'signal, the binary one at the J input terminal of flip-flop 57 is transmitted therethrough to an input terminal of AND gate connected to the Q output terminal of flip-flop 57. Thus, AND gate 56 is enabled by the signal from flipflop 57. When state detector 32 (see FIG. 2) detects that the output of timer 29 has counted to an appropriate count, detector 32 produces detector signal DFT which becomes true. Therefore AND gate 56 is enabled whereby OR gate 55 produces a second fire command and, as well, counter 51 is decremented. This results in two injections being enabled in two different cylinders by the same distributor pulse and reduces the delay for the second injection by one distributor pulse. Also these injections are separated by a time interval determined by state detector 32 to allow the injector driver to recover from the first injection prior to the second injection.

The FIRE command or signal is supplied to AND gates 66 and 67 as described supra. The other signals supplied to AND gates 66 and 67 are supplied from decoder 61. Decoder 61 operates upon the difference between the REF signal and SERVO signal to determine which cylinder is to be injected by application of the next FIRE pulse. That is, the reference signal REF determines the distributor pulse position relative to the engine cycle while the SERVO signal is determined by the status of the engine operation and determines whether or not the injection timing is advanced and by how much.

Once the FIRE signal and the injector signal have been provided whereby AND gates 66 through 67 set the associated flip-flops 68 and 69, respectively, a drive signal is supplied to injector driver 70 or 71 (which represent two of N injector drivers). These signals, supplied by the flip-flops, remain in the on condition wherein the injector driver remains on until the counter associated with the flip-flop counts to a signal which equals or exceeds the pulse width signal PW. When the counter (effectively a timer) produces a signal which is larger than the PW signal, the digital comparator produces a binary one signal which is supplied to the input K terminal of the associated flip-flop. Consequently, on the next clock signal, the flip-flop is triggered so that the zero output signal is produced and resets the appropriate counter 63 through 65 as well as causing the signal to the appropriate injector driver 70 through 71 to be terminated.

Of course, while the injector drivers are operative, the injector is operative to inject fuel into the overall system. As indicated, the fuel is injected into the system at the appropriate time and for the appropriate time duration so that the proper amount of fuel is injected into the engine relative to the operation of the intake valve. In addition, at most only one injection is made by any injector during the engine cycle. Consequently, emission control is greatly improved and a better operating engine is produced.

Thus, there has been shown and described an electronic fuel injection system and more particularly, a fuel injection system which has greater efficiency in the proper mixing of the injected fuel with air entering an appropriate cylinder. This circuit and system controls the efficiency of the mixture of fuel and air as a direct function of the placement of the injection pulse relative to the engine cycle. This system utilizes standard logic type circuitry and lends itself readily to integrated circuit techniques and technology. While a preferred embodiment has been shown and described, it is understood that those skilled in the art may conceive new or improved versions thereof. However, any modifications, or improvements which fall within the perview of this invention are intended to be included therein.

Having thus described the invention, what is claimed is:

1. In combination,

signal supplying means for supplying signals having varying periodicity,

first means connected to said signal supplying means for producing a first control signal representative of the periodicity of signals supplied thereby,

second means connected to said signal supplying means for producing a second control signal representative of the periodicity of signals supplied thereby,

first counter means for producing a first function signal,

said first counter means connected to said first means to receive said first control signal to establish a first condition in said first counter means,

said first counter means connected to said second means to receive said second control signal to establish a different condition in said first counter means,

timer means for producing a timing signal,

said timer means connected to said second means to receive said second control signal to establish a first condition in said timer means, second counter means for producing a second function signal, said second counter means connected to said second means to receive said control signal to establish a first condition in said second counter means,

said second counter means connected to said timer means to receive said timing signal,

input means for supplying input signals,

said input means connected to said second counter such that said timing signal and said input signals control the operation of said second counter means,

first control means connected to said second means,

to said timing means and to said second counter means to receive said second control signal, said timing signal and said second function signal in order to produce a third function signal representative of the relationship therebetween, and

output control means connected to said first counter means, said input means and said first control means to receive said input signals, said first function signal and said third function signal to produce an output control signal representative of the relationship therebetween.

2. The combination recited in claim 1 wherein said timer means includes feedback means for returning said timing signal to an input of said timer means to establish a maximum timing signal. condition therein.

3. The combination recited in claim 1 including initialization means connected to said output control means to establish initial operating conditions.

4. The combination recited in claim 1 including switch means connected to receive said timing signal from said timer means and said second control signal from said second means,

said switch means connected to supply a timing signal to said second counter means to control the counting by said second counter means.

5. The combination recited in claim 1 including,

comparing means connected to receive said timing signal from said timer means and said second function signal from said second counter means, and to produce a signal representative of the relation therebetween,

said comparing means connected to supply the signal produced thereby to said second counter means.

6. The combination recited in claim 1 wherein said input means includes,

reference signal supplying means,

input signal supplying means,

means for comparing the signals produced by said reference signal supplying means and said input signal supplying means to produce said input signals which represent the, relationship between the signals supplied thereto.

7. The combination recited in claim 1 wherein said output control means includes difference means connected to receive said first function signal and said first control signal in order to produce a difference signal representative of the difference between these signals,

at least one driver means connected to receive said difference signal and said fourth function signal and to be enabled by the concurrent application of said fourth function signal and an appropriate difference signal.

8. The combination recited in claim 7 including decoder means connected to receive said difference signal and to supply a decoded signal to said driver means to select the driver means to be enabled.

9. The combination recited in claim 7 including comparator means,

counter means, and

switch means connected to said driver means,

said counter means connected to receive signals from said switch means in order to control the operation of said counter means, said comparator means connected to receive said input signal and the output signal from said counter means in order to produce a signal which is supplied to said switch means to control the operation thereof. v10. The combination recited in claim 1 wherein said second counter means includes threshold counter means connected to receive said second control signal at one input terminal to establish a first condition in said threshold counter means,

memory means connected to the output of said threshold counter means to receive said second function signal as a memory address signal,

comparator means connected to receive said timing signal and the signal stored in the address in said memory means which is addressed by the memory address signal from said threshold counter, and

gate means for selectively supplying the output signal from said comparator means to another input terminal to establish a different condition in said threshold counter means.

11. The combination recited in claim 1 wherein said first control means includes up/down counter means for producing said third function signal,

comparator means, and

gating means for producing said fourth function signal,

said comparator connected to receive said second function signal from said second counter means and said third function signal from said up/down counter means and to supply a first output signal to said up/down counter means and to said gating means and a second output signal to said gating means,

said gating means producing said fourth function signal in response to concurrent application of said first output signal from said up/down counter means and said second control signal from said second means without affecting said up/down counter means,

said gating means producing said fourth function signal which is returned to said up/down counter means in response to the concurrent application of said second output signal from said up/down counter means and said second control signal from said second means in conjunction with said timing signal.

12. In combination,

means for supplying pulses of varying periodicity,

first logic circuit means connected to receive pulses from said means for supplying pulses to produce at least two control signals representative of said pulses received thereby,

second logic circuit means connected to receive different pulses from said means for supplying pulses and to produce a third control signal representative of the pulses received thereby,

first, second and third counter means for counting said control signals and producing function signals representative thereof,

said first counter means connected to receive said third control signal from said second logic circuit and one of said two control signals from said first logic circuit and to produce a first function signal representative of the signals received thereby,

said second counter means adapted to count toward a prescribed maximum condition at a controlled rate until periodically reset to a prescribed condition by said third control signal and to produce a second function representative of the instantaneous condition thereof,

said third counter means adapted to count at a controlled rate in response to a condition produced in response to at least one of said function signals until reset to a prescribed condition by said third control signal, and

means for receiving said control signals and said function signals to produce an output signal.

13. The combination recited in claim 12 wherein said means for supplying pulses produces a first train of pulses for establishing a timing operation and a second train of pulses for establishing a reference point in said timing operation.

14. The combination recited in claim 12 including logic means having one input terminal connected to said second counter means and one output terminal connected to said third counter means whereby the signal at said one output terminal of said logic means is a function of the signal supplied at said one input terminal of said logic means,

said logic means having a second input terminal connected to said second logic circuit means whereby said logic means is triggered by said third control signal.

15. The combination recited in claim 14 including input means for supplying input signals,

said input means connected to said third counter means whereby said input signals and at least one of said function signals produce said condition which permits counting by said third counter means.

16. The combination recited in claim 15 including feedback means connected from the output of said third counter means to the input thereof, said feedback means connected to said second counter means to receive said second function signal whereby the operation of said feedback means is controlled, and

gate means having input terminals connected to receive signals from said input means, said logic means and said feedback means,

said gate means having an output terminal connected to said third counter means to control the counting thereof.

17. The combination recited in claim 14 wherein said input means includes,

reference signal supplying means for establishing a threshold signal representative of a prescribed pulsewidth,

input signal supplying means for establishing a signal of an actual pulsewidth, and

means for comparing the signals supplied by said reference signal supplying means and said input signal supplying means in order to produce an output signal representative of the relationship therebetween.

18. The combination recited in claim 12 including further counting means,

comparision means connected to said further counting means and to said third counter means to compare the signals supplied thereby and to produce output signals representative of the relative status of said signals supplied,

first means for selectively supplying one output signal produced by said comparison means to said further counting means,

logic means,

second means for selectively supplying another output signal produced by said comparison means to said logic means,

each of said first and second means connected to receive said third control signal which enables said first and second means,

first gate means for selectively supplying the output signal from said logic means to output means, to said further counting means and to said logic means in response to said second function signal produced by said second counter means, and

second gate means for selectively supplying said one output signal to said output means in response to said third control signal.

19. The combination recited in claim 18 including comparator means connected between said second and third counter means to provide a signal which controls said condition.

20. The combination recited in claim 19 wherein said means for receiving includes further counter means connected to selectively count said third control signals, and further comparator means connected to said further counter means and to said third counter means to produce a controlling signal representative of the relationship between the signals produced by each of said third and said further counter means to control the production of output signal.

21. The combination recited in claim 20 including subtractor means connected to said first counter means and said further counter means to subtract the signals produced thereby, and decoder means connected to said subtractor to produce enabling signals at selected ones of a plurality of utilization devi'ces.

l l I! 

1. In combination, signal supplying means for supplying signals having varying periodicity, first means connected to said signal supplying means for producing a first control signal representative of the periodicity of signals supplied thereby, second means connected to said signal supplying means for producing a second control signal representative of the periodicity of signals supplied thereby, first counter means for producing a first function signal, said first counter means connected to said first means to receive said first control signal to establish a first condition in said first counter means, said first counter means connected to said second means to receive said second control signal to establish a different condition in said first counter means, timer means for producing a timing signal, said timer means connected to said second means to receive said second control signal to establish a first condition in said timer means, second counter means for producing a second function signal, said second counter means connected to said second means to receive said control signal to establish a first condition in said second counter means, said second counter means connected to said timer means to receive said timing signal, input means for supplying input signals, said input means connected to said second counter such that said timing signal and said input signals control the operation of said second counter means, first control means connected to said second means, to said timing means and to said second counter means to receive said second control signal, said timing signal and said second function signal in order to produce a third function signal representative of the relationship therebetween, and output control means connected to said first counter means, said input means and said first control means to receive said input signals, said first function signal and said third function signal to produce an output control signal representative of the relationship therebetween.
 2. The combination recited in claim 1 wherein said timer means includes feedback means for returning said timing signal to an input of said timer means to establish a maximum timing signal condition therein.
 3. The combination recited in claim 1 including initialization means connected to said output control means to establish initial operating conditions.
 4. THe combination recited in claim 1 including switch means connected to receive said timing signal from said timer means and said second control signal from said second means, said switch means connected to supply a timing signal to said second counter means to control the counting by said second counter means.
 5. The combination recited in claim 1 including, comparing means connected to receive said timing signal from said timer means and said second function signal from said second counter means, and to produce a signal representative of the relation therebetween, said comparing means connected to supply the signal produced thereby to said second counter means.
 6. The combination recited in claim 1 wherein said input means includes, reference signal supplying means, input signal supplying means, means for comparing the signals produced by said reference signal supplying means and said input signal supplying means to produce said input signals which represent the relationship between the signals supplied thereto.
 7. The combination recited in claim 1 wherein said output control means includes difference means connected to receive said first function signal and said first control signal in order to produce a difference signal representative of the difference between these signals, at least one driver means connected to receive said difference signal and said fourth function signal and to be enabled by the concurrent application of said fourth function signal and an appropriate difference signal.
 8. The combination recited in claim 7 including decoder means connected to receive said difference signal and to supply a decoded signal to said driver means to select the driver means to be enabled.
 9. The combination recited in claim 7 including comparator means, counter means, and switch means connected to said driver means, said counter means connected to receive signals from said switch means in order to control the operation of said counter means, said comparator means connected to receive said input signal and the output signal from said counter means in order to produce a signal which is supplied to said switch means to control the operation thereof.
 10. The combination recited in claim 1 wherein said second counter means includes threshold counter means connected to receive said second control signal at one input terminal to establish a first condition in said threshold counter means, memory means connected to the output of said threshold counter means to receive said second function signal as a memory address signal, comparator means connected to receive said timing signal and the signal stored in the address in said memory means which is addressed by the memory address signal from said threshold counter, and gate means for selectively supplying the output signal from said comparator means to another input terminal to establish a different condition in said threshold counter means.
 11. The combination recited in claim 1 wherein said first control means includes up/down counter means for producing said third function signal, comparator means, and gating means for producing said fourth function signal, said comparator connected to receive said second function signal from said second counter means and said third function signal from said up/down counter means and to supply a first output signal to said up/down counter means and to said gating means and a second output signal to said gating means, said gating means producing said fourth function signal in response to concurrent application of said first output signal from said up/down counter means and said second control signal from said second means without affecting said up/down counter means, said gating means producing said fourth function signal which is returned to said up/down counter means in response to the concurrent application of said second output signal from said up/down counter means and said seCond control signal from said second means in conjunction with said timing signal.
 12. In combination, means for supplying pulses of varying periodicity, first logic circuit means connected to receive pulses from said means for supplying pulses to produce at least two control signals representative of said pulses received thereby, second logic circuit means connected to receive different pulses from said means for supplying pulses and to produce a third control signal representative of the pulses received thereby, first, second and third counter means for counting said control signals and producing function signals representative thereof, said first counter means connected to receive said third control signal from said second logic circuit and one of said two control signals from said first logic circuit and to produce a first function signal representative of the signals received thereby, said second counter means adapted to count toward a prescribed maximum condition at a controlled rate until periodically reset to a prescribed condition by said third control signal and to produce a second function representative of the instantaneous condition thereof, said third counter means adapted to count at a controlled rate in response to a condition produced in response to at least one of said function signals until reset to a prescribed condition by said third control signal, and means for receiving said control signals and said function signals to produce an output signal.
 13. The combination recited in claim 12 wherein said means for supplying pulses produces a first train of pulses for establishing a timing operation and a second train of pulses for establishing a reference point in said timing operation.
 14. The combination recited in claim 12 including logic means having one input terminal connected to said second counter means and one output terminal connected to said third counter means whereby the signal at said one output terminal of said logic means is a function of the signal supplied at said one input terminal of said logic means, said logic means having a second input terminal connected to said second logic circuit means whereby said logic means is triggered by said third control signal.
 15. The combination recited in claim 14 including input means for supplying input signals, said input means connected to said third counter means whereby said input signals and at least one of said function signals produce said condition which permits counting by said third counter means.
 16. The combination recited in claim 15 including feedback means connected from the output of said third counter means to the input thereof, said feedback means connected to said second counter means to receive said second function signal whereby the operation of said feedback means is controlled, and gate means having input terminals connected to receive signals from said input means, said logic means and said feedback means, said gate means having an output terminal connected to said third counter means to control the counting thereof.
 17. The combination recited in claim 14 wherein said input means includes, reference signal supplying means for establishing a threshold signal representative of a prescribed pulsewidth, input signal supplying means for establishing a signal of an actual pulsewidth, and means for comparing the signals supplied by said reference signal supplying means and said input signal supplying means in order to produce an output signal representative of the relationship therebetween.
 18. The combination recited in claim 12 including further counting means, comparision means connected to said further counting means and to said third counter means to compare the signals supplied thereby and to produce output signals representative of the relative status of said signals supplied, first means for selectively supplying one output signal produced by said cOmparison means to said further counting means, logic means, second means for selectively supplying another output signal produced by said comparison means to said logic means, each of said first and second means connected to receive said third control signal which enables said first and second means, first gate means for selectively supplying the output signal from said logic means to output means, to said further counting means and to said logic means in response to said second function signal produced by said second counter means, and second gate means for selectively supplying said one output signal to said output means in response to said third control signal.
 19. The combination recited in claim 18 including comparator means connected between said second and third counter means to provide a signal which controls said condition.
 20. The combination recited in claim 19 wherein said means for receiving includes further counter means connected to selectively count said third control signals, and further comparator means connected to said further counter means and to said third counter means to produce a controlling signal representative of the relationship between the signals produced by each of said third and said further counter means to control the production of output signal.
 21. The combination recited in claim 20 including subtractor means connected to said first counter means and said further counter means to subtract the signals produced thereby, and decoder means connected to said subtractor to produce enabling signals at selected ones of a plurality of utilization devices. 